HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 727

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
18.3.9
SISCMR is an 8-bit readable/writable register that selects smart card interface functions.
Bit
7
6
5
4
3
2
Bit Name
LCB
PB
SDIR
SINV
Smart Card Mode Register (SISCMR)
Initial
Value
0
0
0
0
0
0
Initial value:
R/W:
R/W
R
R/W
R/W
R
R/W
R/W
Bit:
7
0
R
-
Description
Reserved
This bit is always read as 0. The write value should always be
0.
Last Character
When this bit is set to 1, the guardtime is 2 etu, and the setting
of the guard extension register is invalid.
0: The guardtime is determined by the guard register value
1: The guardtime is 2 etu
Protocol
Selects the T = 0 or T = 1 protocol.
0: The smart card interface operates according to the T = 0
1: The smart card interface operates according to the T = 1
Reserved
This bit is always read as 0. The write value should also always
be 0.
Smart Card Data Transfer Direction
Selects the format for serial/parallel conversion.
0: Transmit the SITDR contents LSB-first
1: Transmit the SITDR contents MSB-first
Smart Card Data Inversion
Specifies inversion of the data logic level. In combination with
the function of bit 3, used for transmission to and reception from
an inverse convention card. SINV does not affect the parity bit.
0: Transmit the SITDR contents without change
1: Invert and transmit the SITDR data
LCB
protocol
protocol
Received data is stored in SIRDR LSB-first.
Received data is stored in SIRDR MSB-first.
Store received data in SIRDR without change
Invert and store received data in SIRDR
R/W
6
0
R/W
PB
5
0
4
0
R
-
SDIR
R/W
3
0
Rev. 2.00 Feb. 12, 2010 Page 643 of 1330
SINV
R/W
2
0
RST
R/W
1
0
SMIF
R/W
1
0
REJ09B0554-0200

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