HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 699

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 17 Serial Communication Interface with FIFO (SCIF)
(1) Data Transfer Format
A fixed 8-bit data format is used. No parity bit can be added.
(2) Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCIF_CLK pin can be selected as the SCIF's serial clock,
according to the settings of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For
details of SCIF clock source selection, see table 17.5.
When the SCIF is operated on an internal clock, the synchronization clock is output from the
SCIF_CLK pin. Eight synchronization clock pulses are output in the transfer of one character, and
when no transfer is performed the clock is fixed high. When an internal clock is selected in a
receive operation only, as long as the RE bit in SCSCR is set to 1, clock pulses are output until the
number of receive data bytes in the receive FIFO data register reaches the receive trigger number.
(3) SCIF Initialization (Synchronous Mode)
Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0,
then initialize the SCIF as described below.
When changing the operating mode or transfer format, etc., the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0,
SCTSR is initialized. Note that clearing the RE bit to 0 does not initialize the RDF, PER, FER, or
ORER flag state or change the contents of SCFRDR.
Rev. 2.00 Feb. 12, 2010 Page 615 of 1330
REJ09B0554-0200