HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 519

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(2) Bus Modes
There are two bus modes: cycle steal mode and burst mode. The bus mode is selected for each
channel with the TM bit in CHCR0 to CHCR7.
• Cycle Steal Mode
In cycle steal mode, the DMAC releases the bus to the CPU at the end of each transfer-unit (8-
bit, 16-bit, 32-bit, 64-bit, or 32-byte) transfer. When the next transfer request is issued, the
DMAC reacquires the bus from the CPU and carries out another transfer-unit transfer. At the
end of this transfer, the bus is again given to the CPU. This is repeated until the transfer end
condition is satisfied.
In cycle steal mode, areas for transfer has no limitation by the settings of transfer request
source, transfer source, and transfer destination.
Figure 11.10 shows an example of DMA transfer timing in cycle steal mode. The following
transfer conditions are used in this example:
⎯ Dual address mode
⎯ DREQ level detection
D31–D0
A26–A0
DACK
CKIO
Figure 11.9 Example of Transfer Timing in Dual Address Mode
CSn
WE
RD
Transfer from external memory space to external memory space
Data read cycle
Transfer source
(1st cycle)
address
Data write cycle
Transfer destination
(2nd cycle)
address
Rev. 2.00 Feb. 12, 2010 Page 435 of 1330
REJ09B0554-0200