HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 394

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 Bus State Controller (BSC)
10.6.3
SRAM Interface
(1) Basic Timing
The strobe signals for the SRAM interface of this LSI are output primarily based on the SRAM
connection. Figure 10.6 shows the basic timing of SRAM interface. A no-wait normal access is
completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus
cycle. The CSn signal is asserted at the rising edge of the clock in the T1 state, and negated at the
rising edge of the clock after the T2 state. Therefore, there is no negation period in the case of
access at minimum pitch.
When reading, specifying an access size is not needed. The output addresses on the address pins
(A25 to A0) are correct, but since the access size is not specified, 32-bit data is always output
when a 32-bit device is in use, and 16-bit data is output when a 16-bit device is in use. When
writing, only the WEn signal corresponding to the byte to be written is asserted. For details, see
section 10.6.1, Endian/Access Size and Data Alignment.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed in wraparound mode on the data at the 32-byte boundary. The bus is not
released during this transfer.
Rev. 2.00 Feb. 12, 2010 Page 310 of 1330
REJ09B0554-0200