HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 947

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

In some applications, an undefined amount of data will received from an external HSPI device. If
this is the case, follow the following procedure:
1. Set up the module for the required HSPI transfer characteristics (master/slave, clock polarity
2. Fill the transmit FIFO with the data to transmit. Enable the receive FIFO not empty interrupt.
3. Respond to the receive FIFO not empty interrupt and read data from the receive FIFO until it is
4. Disable the module when the transfer is to stop.
23.4.4
The following diagrams explain the timing relationship of all shift and sample processes in the
HSPI. Figure 23.3 shows the conditions when FBS = 0, while figure 23.4 shows the conditions
when FBS = 1. It can be seen that if CLKP in SPCR is 0 then transmit data is shifted on the falling
edge of HSPI_CLK and receive data is sampled on the rising edge. The opposite is true when
CLKP = 1.
etc.) and enable FIFO mode.
empty. Write more data to the transmit FIFO if required.
Timing Diagrams
HSPI_CLK (CLKP = 0)
HSPI_CLK (CLKP = 1)
Data transfer cycle
HSPI_RX
HSPI_CS
HSPI_TX
Figure 23.3 Timing Conditions when FBS = 0
MSB
MSB
1
2
6
6
3
5
5
4
4
4
5
3
3
Rev. 2.00 Feb. 12, 2010 Page 863 of 1330
6
2
2
7
1
1
LSB
LSB
8
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REJ09B0554-0200