HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 50

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 20 Serial Sound Interface (SSI) Module ............................................. 707
20.1 Features............................................................................................................................ 707
20.2 Input/Output Pins ............................................................................................................. 708
20.3 Register Descriptions ....................................................................................................... 709
20.4 Operation ......................................................................................................................... 722
20.5 Usage Note....................................................................................................................... 741
Section 21 USB Host Module (USB) ............................................................... 743
21.1 Features............................................................................................................................ 743
21.2 Input/Output Pins ............................................................................................................. 745
21.3 Register Descriptions ....................................................................................................... 745
Rev. 2.00 Feb. 12, 2010 Page xlviii of lxxxii
REJ09B0554-0200
19.7.2 Restriction 2........................................................................................................ 704
20.3.1 Control Register (SSICR) ................................................................................... 710
20.3.2 Status Register (SSISR) ...................................................................................... 716
20.3.3 Transmit Data Register (SSITDR) ...................................................................... 721
20.3.4 Receive Data Register (SSIRDR) ....................................................................... 721
20.4.1 Bus Format.......................................................................................................... 722
20.4.2 Non-Compressed Modes..................................................................................... 722
20.4.3 Compressed Modes............................................................................................. 731
20.4.4 Operation Modes................................................................................................. 733
20.4.5 Transmit Operation ............................................................................................. 734
20.4.6 Receive Operation............................................................................................... 738
20.4.7 Serial Clock Control ........................................................................................... 741
20.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation .......... 741
20.5.2 Notes on Stopping SSI Module Slave Mode Operation...................................... 742
21.3.1 Host Controller Interface Revision Register (HcRevision)................................. 748
21.3.2 Control Register (HcControl).............................................................................. 748
21.3.3 Command Status Register (HcCommandStatus) ................................................ 752
21.3.4 Interrupt Status Register (HcInterruptStatus)...................................................... 754
21.3.5 Interrupt Enable Register (HcInterruptEnable) ................................................... 756
21.3.6 Interrupt Disable Register (HcInterruptDisable)................................................. 758
21.3.7 Host Controller Communication Area Pointer Register (HcHCCA) .................. 760
21.3.8 Period Current ED Pointer Register (HcPeriodCurrentED)................................ 760
21.3.9 Control Head ED Pointer Register (HcControlHeadED).................................... 761
21.3.10 Control Current ED Pointer Register (HcControlCurrentED) ............................ 761
21.3.11 Bulk Head ED Pointer Register (HcBulkHeadED)............................................. 762
21.3.12 Bulk Current ED Pointer Register (HcBulkCurrentED) ..................................... 762
21.3.13 Done Queue Head Pointer Register (HcDoneHead) ........................................... 763
21.3.14 Frame Interval Register (HcFmInterval)............................................................. 764
21.3.15 Frame Remaining Register (HcFmRemaining) .................................................. 765
21.3.16 Frame Number Register (HcFmNumber) ........................................................... 766