HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1214

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Note: n = 31 to 0
31.2.9
BRCR is a 16-bit readable/writable register that specifies (1) whether channels A and B are to be
used as two independent channels or in a sequential condition, (2) whether the break is to be
effected before or after instruction execution, (3) whether the BDRB register is to be included in
the channel B break conditions, and (4) whether the user break debug function is to be used.
BRCR also contains condition match flags. The CMFA, CMFB, and UBDE bits in BRCR are
initialized to 0 by a power-on reset, but retain their value in standby mode. The PCBA, DBEB,
PCBB, and SEQ bits are undefined after a power-on reset or manual reset, so these bits should be
initialized by software as necessary.
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 1130 of 1330
REJ09B0554-0200
Bit
31 to 0
Bit
15
14
R/W:
Bit:
CMFA
Break Control Register (BRCR)
Bit Name
BDMB31 to
BDMB0
Bit Name
CMFA
CMFB
R/W
15
0
CMFB
R/W
14
0
13
R
0
-
Initial Value
—
Initial Value
0
0
12
R
0
-
11
R
0
-
PCBA
R/W
10
-
R/W
R/W
R/W
R/W
R/W
R
9
0
-
Description
Break Data Mask B
These bits specify whether the corresponding bit of
the channel B break data Bn set in BDRB is to be
masked.
0: Channel B break data Bn is included in break
1: Channel B break data Bn is masked, and not
Description
Condition Match Flag A
Set to 1 when a break condition set for channel A
is satisfied. This flag is not cleared to 0. To confirm
that the flag is set again after once being set, it
should be cleared with a write.
0: Channel A break condition does not matched
1: Channel A break condition has matched
Condition Match Flag B
Set to 1 when a break condition set for channel B
is satisfied. This flag is not cleared to 0. To confirm
that the flag is set again after once being set, it
should be cleared with a write.
0: Channel B break condition is not matched
1: Channel B break condition match has occurred
conditions
included in break conditions
R
8
0
-
DBEB
R/W
7
-
PCBB
R/W
6
-
R
5
0
-
4
0
R
-
SEQ
R/W
3
-
2
0
R
-
R
1
0
-
UBDE
R/W
0
0