HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 360

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 Feb. 12, 2010 Page 276 of 1330
REJ09B0554-0200
Bit
22
21
20
19
18
17
16
Bit
Name
A5B2
A5B1
A5B0
A4W2
A4W1
A4W0
⎯
Initial
Value
1
1
1
1
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Area 5 Burst Pitch
These bits specify the number of wait cycles to be
inserted for the second and following data accesses in
burst transfer when area 5 is specified as burst ROM
area.
000:
001:
010:
011:
100:
101:
110:
111:
Area 4 Wait Control
These bits specify the number of wait cycles to be
inserted for area 4. For the case where an MPX interface
setting is made, see table 10.7.
000:
001:
010:
011:
100:
101:
110:
111:
Reserved
This bit is always read as 0. The write value should
always be 0.
Inserted wait cycles
0
1
2
3
4
5
6
7
Inserted wait cycles
0
1
2
3
6
9
12
15
RDY pin
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
RDY pin
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled