HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 128

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2.2.3
The control registers are 32 bits long. They consist of the status register (SR), global base register
(GBR), saved status register (SSR), saved program counter (SPC), vector base register (VBR),
saved general register 15 (SGR), and debug base register (DBR). SR and GBR can be accessed in
both processing modes, but SSR, SPC, VBR, SGR, and DBR can only be accessed in privileged
mode.
Status Register (SR):
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 44 of 1330
REJ09B0554-0200
Bit
31
30
29
28
R/W:
R/W:
Bit:
Bit:
Control Registers
Bit Name Initial Value R/W
—
MD
RB
BL
R/W
FD
31
15
R
0
0
-
R/W
MD
30
14
-
R
1
0
0
1
1
1
R/W
RB
29
13
R
1
0
-
R/W
BL
28
12
R
1
0
-
27
11
R
R
0
0
-
-
R
R/W
R/W
R/W
26
10
R
R
-
0
-
0
1: R0_BANK1 to R7_BANK1 are accessed as general r
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Processing Mode
Selects the processing mode.
0: User mode (Some instructions cannot be executed
1: Privileged mode
Privileged Mode General Register Bank Soecification
Bit
This bit is set to 1 by an exception or interrupt.
0: R0_BANK0 to R7_BANK0 are accessed as general
Exception/Interrupt Block Bit
This bit is set to 1 by a reset, an exception, or an
interrupt. While this bit is set to 1, an interrupt request
is masked. In this case, this processor enters the reset
state when a general exception other than a user
break occurs.
R/W
25
M
R
-
0
9
-
registers R0 to R7 and R0_BANK1 to R7_BANK1
can be accessed using LDC/STC instructions
can be accessed using LDC/STC instructions
and some resources cannot be accessed.)
R/W
24
Q
R
0
8
-
-
IMASK3 IMASK2 IMASK1 IMASK0
R/W
23
R
0
7
1
-
R/W
22
R
0
6
1
-
R/W
21
R
0
5
1
-
R/W
20
R
0
4
1
-
19
R
0
3
-
0
R
-
18
R
R
0
2
0
-
-
R/W
17
R
0
1
S
-
-
R/W
16
R
0
0
T
-
-