HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1223

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4. If channels A and B both match independently at virtually the same time, and, as a result, the
5. The PCBA or PCBB bit in BRCR is valid for an instruction access break setting.
6. When the SEQ bit in BRCR is 1, the internal sequential break state is initialized by a channel
7. In the event of conflict between a re-execution type exception and a post-execution break in a
8. A post-execution break is classified as a completed-type exception. Consequently, in the event
31.5
The user break debug support function enables the processing used in the event of a user break
exception to be changed. When a user break exception occurs, if the UBDE bit in BRCR is set to
1, the DBR value will be used as the branch destination address instead of [VBR + offset]. The
value of R15 is saved in SGR regardless of the value of the UBDE bit in BRCR or the type of
exception event. A flowchart of the user break debug support function is shown in figure 31.2.
⎯ In the case of an RTE delay slot
⎯ If an interrupt or exception is accepted with the BL bit cleared to 0, the value of the BL bit
SPC value is the same for both user break interrupts, only one user break interrupt is generated,
but both the CMFA bit and the CMFB bit are set. For example:
110 Instruction (post-execution instruction break on channel A) → SPC = 112, CMFA = 1
112 Instruction (pre-execution instruction break on channel B) → SPC = 112, CMFB = 1
B condition match. For example: A → A → B (user break generated) → B (no break
generated)
multistep instruction, the re-executing-type exception is generated. In this case, the CMF bit
may or may not be set to 1 when the break condition occurs.
of conflict between a completed-type exception and a post-execution break, the post-execution
break is suppressed in accordance with the priorities of the two events. For example, in the
case of conflict between a TRAPA instruction and a post-execution break, the user break is
suppressed. However, in this case, the CMF bit is set by the occurrence of the break condition.
The BL bit value before execution of a delay slot instruction is the same as the BL bit value
before execution of an RTE instruction. The BL bit value after execution of a delay slot
instruction is the same as the first BL bit value for the first instruction executed on
returning by means of an RTE instruction (the same as the value of the BL bit in SSR
before execution of the RTE instruction).
before execution of the first instruction of the exception handling routine is 1.
User Break Debug Support Function
Rev. 2.00 Feb. 12, 2010 Page 1139 of 1330
REJ09B0554-0200