HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 357

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Read
Write
DMA read
(memory →
device)
DMA write
(device →
memory)
Table 10.7 Idle Insertion between Accesses
Preceding
Cycle
DMA in the table indicates DMA single-address transfer. DMA dual-address transfer is in
accordance with the CPU.
M, D: Idle wait always inserted by WCR1
M:
D:
Notes: When synchronous DRAM is used in RAS down mode, bits DMAIW2 to DAMIW0 and bits
(M(1): One cycle inserted in MPX access even if WCR1 is cleared to 0)
Idle cycles according to setting of AnIW2 to AnIW0 (areas 0 to 6)
Idle cycles according to setting of DMAIW2 to DMAIW0
A3IW2 to A3IW0 should be both 000.
1. Inserted when device is switched
2. On the MPX interface, a WCR1 idle wait may be inserted before an access (either read
or write) to the same area after a write access. An example of idle wait insertion in
accesses to the same area is shown below.
(a) Synchronous DRAM set to RAS down mode
(b) Synchronous DRAM accessed by on-chip DMAC
Under conditions other than conditions (a) and (b) above, an idle wait is also inserted
between an MPX interface write access and an immediately following access to the
same area.
Under above conditions (a) and (b), an idle wait may be inserted in a same-area access
following an MPX interface write access, depending on the synchronous DRAM pipeline
access situation. An idle wait is not inserted when the WCR1 setting is 0. The setting for
the number of idle state cycles inserted after a power-on reset is the default value of 15
(the maximum value), so ensure that the optimum value is set.
CPU DMA
D
Read
D
Same Area
M
M
D
CPU DMA
Write
M
M
D*
1
M
M
M
D
CPU DMA
Following Cycle
Read
M
M
M
D
Different Area
Rev. 2.00 Feb. 12, 2010 Page 273 of 1330
M
M
M
D
CPU DMA
Write
M
M
M
D
M (1)
*
Same
Area
MPX
Address
Output
2
REJ09B0554-0200
Different
Area
MPX
Address
Output
M (1)
M
M (1)
D (1)