HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 491

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
Bit
26
25
24
23
22
21 to 18 —
17
16
Bit Name
REX2
REX1
REX0
R/A3
R/A2
RPR1
RPR0
Initial Value
0
0
0
0
0
All 0
0
0
R/W
R
R
R
R/W
R/W
R
R/W
R/W
Description
Channel 2 Request Reception*
0: Channel 2 does not accept a transfer request
1: Channel 2 accepts a transfer request
Channel 1 request Reception*
0: Channel 1 does not accept a transfer request
1: Channel 1 accepts a transfer request
Channel 0 Request Reception*
0: Channel 0 does not accept a transfer request
1: Channel 0 accepts a transfer request
DRAK3/DACK3 Select
0: Outputs DRAK3
1: Outputs DACK3
DRAK2/DACK2 Select
0: Outputs DRAK2
1: Outputs DACK2
Reserved
These bits are always read as 0. The write value
should always be 0.
Request Priority 1 and 0
Select the request priority order.
00: DMABRG*
01: DMABRG*
10: DREQ0 > DMABRG*
11: Round-robin (Initial setting: DMABRG*
Note: Setting RPR[1:0] = 01 will make all
DREQ3
DREQ3
DREQ3
DREQ0 > DREQ1 > DREQ2 > DREQ3)
channels disabled to receive a transfer
request from on-chip peripheral modules
except for LCDC, HAC, SSI, USB, and
TMU or an external request (DREQ), after
having accepted a DMABRG request
(REX0 = 1). When the DMABRG request
is cleared (REX0 = 0), transfer requests
are acceptable.
Rev. 2.00 Feb. 12, 2010 Page 407 of 1330
1
1
> DREQ0 > DREQ1 > DREQ2 >
> DREQ0 > DREQ1 > DREQ2 >
1
> DREQ1 > DREQ2 >
4
*
4
4
*
*
5
*
7
6
REJ09B0554-0200
*
7
7
1
>

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