HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 190

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number

HD6417760BL200AV

Description

SH4 7760, 17 X17 256BGA, LCDC, U

Manufacturer

Renesas Electronics America

Series

SuperH® SH7750r

Datasheet

1.D6417760BP200ADV.pdf (1418 pages)

Specifications of HD6417760BL200AV

Core Processor

SH-4

Core Size

32-Bit

Speed

200MHz

Connectivity

Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB

Peripherals

DMA, LCD, POR, WDT

Number Of I /o

69

Program Memory Type

ROMless

Ram Size

48K x 8

Voltage - Supply (vcc/vdd)

1.4 V ~ 1.6 V

Data Converters

A/D 4x10b

Oscillator Type

Internal

Operating Temperature

-40°C ~ 85°C

Package / Case

256-BGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Eeprom Size

-

Program Memory Size

-

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

HD6417760BL200AV

Manufacturer:

Renesas Electronics America

Quantity:

10 000

Company:

Meier Automation Equipment Co., Limited

Meier Automation Equipment Co., Limited

Part Number:

HD6417760BL200AV

Manufacturer:

RENENAS

Quantity:

20 000

Current page: 190 of 1418
Download datasheet (9Mb)

Rev. 2.00 Feb. 12, 2010 Page 106 of 1330

REJ09B0554-0200

Category

Fixed-point

arithmetic

instructions

Logical

instructions

Shift

instructions

Functional

71

72

73

74

75

76

77

80

81

82

83

84

85

86

87

88

89

90

91

94

95

96

97

98

99

100

101

No.

68

69

70

78

79

92

93

Instruction

MAC.L

MAC.W

MUL.L

MULS.W

MULU.W

NEG

NEGC

SUB

SUBC

SUBV

AND

AND

AND.B

NOT

OR

OR

OR.B

TAS.B

TST

TST

TST.B

XOR

XOR

XOR.B

ROTL

ROTR

ROTCL

ROTCR

SHAD

SHAL

SHAR

SHLD

SHLL

SHLL2

Rm,Rn

Rm,Rn

Rm,Rn

Rm,Rn

Rm,Rn

Rm,Rn

Rm,Rn

#imm,@(R0,GBR) CO

Rm,Rn

Rm,Rn

#imm,R0

#imm,@(R0,GBR) CO

@Rn

Rm,Rn

#imm,R0

#imm,@(R0,GBR) CO

Rm,Rn

#imm,R0

#imm,@(R0,GBR) CO

Rn

Rn

Rm,Rn

Rn

Rn

Rm,Rn

Rn

Rn

@Rm+,@Rn+

@Rm+,@Rn+

Rm,Rn

Rm,Rn

#imm,R0

Rn

Rn

CO

CO

EX

EX

EX

EX

EX

EX

EX

EX

CO

MT

MT

EX

EX

EX

EX

EX

EX

EX

EX

EX

EX

Instruc-

tion

Group

CO

CO

CO

EX

EX

EX

EX

Issue

Rate

2

2

2

2

2

1

1

1

1

1

4

1

1

1

4

5

1

1

3

1

1

4

1

1

1

1

1

1

1

1

1

1

1

1

4/4

4/4

1

1

1

1

1

4

1

1

1

4

5

1

1

3

1

1

4

1

1

1

1

1

1

1

1

Latency

2/2/4/4

2/2/4/4

4/4

1

1

1

1

#34

#34

#1

#1

#1

#1

#1

#6

#1

#1

#1

#6

#7

#1

#1

#5

#1

#1

#6

#1

#1

#1

#1

#1

#1

#1

#1

Execution

Pattern

#35

#35

#34

#1

#1

#1

#1

F1

F1

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Stage Start Cycles

F1

F1

F1

—

—

—

—

4

4

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

4

4

4

—

—

—

—

Lock

2

2

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

2

2

2

—

—

—

—

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