HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 780

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
Section 19 I
3. The slave device generates an interrupt by SDT (bit 2) indicating 1-byte data transfer end at the
4. To end data transfer, set FSB (bit 1) to 1 in the master control register in the master device to
The timings of (1) to (3) in figure 19.10 are generated at the falling edge of the clock signal.
Rev. 2.00 Feb. 12, 2010 Page 696 of 1330
REJ09B0554-0200
reads receive data. If this processing is delayed, the slave device extends the SCL period to
suspend data transmission. (in the timing of (3) in figure 19.10.)
eighth clock (in the timing of (2) in figure 19.10) and an interrupt by SDE (bit 3) indicating
data empty at the ninth clock (in the timing of (1) in figure 19.10). Clear SDE to 0 after writing
slave transmit data to TXD.
output a transfer end (force stop). When the last bit of a byte is transmitted/received, the I
module latches the FSB value and enters the stop state. Therefore, to stop the transfer after a
specified byte data is transferred, the FSB bit must be set before the last byte is transferred. If
the last byte is not correct, the protocol layer notifies the slave device that re-transmission is
needed.
SDA
SCL
SDA
(Master output)
SDA
(Slave output)
Master IRQ
Slave IRQ
2
C Bus Interface
Figure 19.10 Data Receive Mode Timing Chart
9
(1)
bit7
1
bit6
2
bit5
3
bit4
4
bit3
5
bit2
6
bit1
7
bit0
8
(2)
(3)
ACK
9
(1)
bit7
1
2
C

Related parts for HD6417760BL200AV