HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 754

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 I
Note: * This bit can be written or read. When 0 is written to, the bit is initialized. When 1 is written
Rev. 2.00 Feb. 12, 2010 Page 670 of 1330
REJ09B0554-0200
Bit
2
1
0
to, it is ignored.
Bit Name
SDT
SDR
SAR
2
C Bus Interface
Initial Value
0
0
0
R/W
R/W*
R/W*
R/W*
Description
Slave Data Transmitted
A byte of data has been transmitted on the bus.
This status bit becomes active after the falling
edge of SCL during the last data bit.
Slave Data Received
A byte of data has been received from the bus
and is available in the receive data register. This
bit becomes active after the falling edge of SCL
during the last data bit. After data has been read
from the ICRXD register, this bit must be reset in
single buffer mode. This bit is not used in the
FIFO buffer mode.
When SDBS is set to 1, SCL will be held low from
the moment the receive data register acquires the
data packet up until SDR is cleared.
Slave Address Received
Indicates that the slave has recognized its own
address on the bus (defined by the contents of
the slave address register). If the general call
acknowledgement enable bit in the slave control
register is enabled, then this status bit could also
indicate the reception of a general call address on
the bus. In that case, bit GCAR of this register is
used to differentiate the receipt of a general call
address. Bit STM indicates whether the access is
a read (high) or a write (low). This status becomes
active after the falling edge of SCL during the last
address bit. The slave holds SCL low at the start
of the ACK phase until this bit is reset by
software.