HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 220

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.4.5
When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise. The
problem is that, when a number of virtual addresses are mapped onto a single physical address, the
same physical address data is recorded in a number of cache entries, and it becomes impossible to
guarantee data integrity. This problem does not occur with the instruction TLB and instruction
cache because data is only read in these cases. In the SH-4, entry specification is performed using
bits 13 to 5 of the virtual address in order to achieve fast operand cache operation. However, bits
13 to 10 of the virtual address in the case of a 1-Kbyte page, and bits 13 and 12 of the virtual
address in the case of a 4-Kbyte page, are subject to address translation. As a result, bits 13 to 10
of the physical address after translation may differ from bits 13 of 10 of the virtual address.
Consequently, the following restrictions apply to the recording of address translation information
in UTLB entries.
• When address translation information whereby a number of 1-Kbyte page UTLB entries are
• When address translation information whereby a number of 4-Kbyte page UTLB entries are
• Do not use 1-Kbyte page UTLB entry physical addresses with UTLB entries of a different
• Do not use 4-Kbyte page UTLB entry physical addresses with UTLB entries of a different
The above restrictions apply only when performing accesses using the cache. When cache index
mode is used, VPN[25] is used for the entry address instead of VPN[13], and therefore the above
restrictions apply to VPN[25].
Note: When multiple items of address translation information use the same physical memory to
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translated into the same physical address is recorded in the UTLB, ensure that the VPN[13:10]
values are the same.
translated into the same physical address is recorded in the UTLB, ensure that the VPN[13:12]
values are the same.
page size.
page size.
provide for future expansion of the SuperH RISC engine family, ensure that the
VPN[20:10] values are the same. Also, do not use the same physical address for address
translation information of different page sizes.
Avoiding Synonym Problems