HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 869

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The Controller Area Network 2 (HCAN2) is a module that controls the Controller Area Network
(CAN) provided for realtime communication in automobiles or industrial equipment systems. For
details on the CAN specification, refer to the CAN Specification Version 2.0, Robert Bosch
GmbH, 1991.
The section places no constraints upon the implementation of the HCAN2 module in terms of
process, packaging or power supply criteria. These issues are resolved appropriately in
implementation specifications.
22.1
• Supports CAN specification 2.0A/2.0B and ISO-11898:
• 31 programmable transmit/receive Mailboxes and one receive-only Mailbox
• Sleep mode for low power consumption and automatic recovery from sleep mode by detecting
• Programmable receive filter masks (standard identifier and extended identifier) are supported
• Programmable CAN data rate up to 1 Mbit/s
• Transmit message queuing with internal priority sorting mechanism against a priority inversion
• Data buffer access without using handshake
• Flexible CPU interface
• Flexible interrupt structure
• A 16-bit free running timer with flexible clock sources and pre-scaler, timer compare match
• Supports flexible time stamp function for both transmission and reception (the stamp timing is
22.2
22.2.1
HCAN2 offers a flexible and sophisticated method for the organization and control of CAN
frames, which is compliant to CAN2.0B Active and ISO-11898. The module is formed from 5
different functional entities. These are the Micro Processor Interface (MPCI), Mailbox, Mailbox
Control, Timer and CAN Interface. The figure below shows the block diagram of the module. The
bus interface timing is designed based on SH internal bus interface.
the CAN bus being active
by all Mailboxes
problem of the real time application
register
programmable)
Section 22 Controller Area Network 2 (HCAN2)
Features
Architecture
Block diagram
Rev. 2.00 Feb. 12, 2010 Page 785 of 1330
REJ09B0554-0200