HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 204

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Memory Management Unit (MMU)
Only when the P0, P3, and U0 areas are mapped onto external memory space by means of the
TLB, addresses H'1C00 0000 to H'1FFF FFFF of area 7 in the external memory space are
allocated to the control register area. This enables control registers to be accessed from the U0
area even in user mode. In this case, the C bit for the corresponding page must be cleared to 0.
P1, P2, and P4 Areas: Address translation using the TLB cannot be performed for the P1, P2, or
P4 area (except for the store queue area). Accesses to these areas are the same as for the physical
address space. The store queue area can be mapped onto any external memory space by the MMU.
However, operation in the case of an exception differs from that for normal P0, U0, and P3 areas.
For details, see section 7.7, Store Queues.
(4) On-Chip RAM Space
In the SH-4, half of the operand cache can be used as on-chip RAM. This can be done by changing
the CCR settings.
When the operand cache is used as on-chip RAM (ORA bit in CCR = 1), addresses H'7C00 0000
to H'7FFF FFFF in the P0 and U0 areas are an on-chip RAM area. Data accesses
(byte/word/longword/quadword) can be used in this area. This area can only be used in RAM
mode.
(5) Address Translation
When the MMU is used, the virtual address space is divided into units called pages, and
translation to physical addresses is carried out in these page units. The address translation table in
external memory contains the physical addresses corresponding to virtual addresses and additional
information such as memory protection codes. Fast address translation is achieved by caching the
contents of the address translation table located in external memory into the TLB. In the SH-4,
basically, the ITLB is used for instruction accesses and the UTLB for data accesses. In the event
of an access to an area other than the P4 area, the accessed virtual address is translated to a
physical address. If the virtual address belongs to the P1 or P2 area, the physical address is
uniquely determined without accessing the TLB. If the virtual address belongs to the P0, U0, or P3
area, the TLB is searched using the virtual address, and if the virtual address is recorded in the
TLB, a TLB hit is made and the corresponding physical address is read from the TLB. If the
accessed virtual address is not recorded in the TLB, a TLB miss exception is generated and
processing switches to the TLB miss exception handling routine. In the TLB miss exception
handling routine, the address translation table in external memory is searched, and the
corresponding physical address and page management information are recorded in the TLB. After
the return from the exception handling routine, the instruction which caused the TLB miss
exception is re-executed.
Rev. 2.00 Feb. 12, 2010 Page 120 of 1330
REJ09B0554-0200