HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 487

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• DMARSRA
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
CH0WEN
CH0RS6
CH0RS5
CH0RS4
CH0RS3
CH0RS2
CH0RS1
CH0RS0
CH1WEN
CH1RS6
CH1RS5
CH1RS4
CH1RS3
CH1RS2
CH1RS1
CH1RS0
CH2WEN
CH2RS6
CH2RS5
CH2RS4
CH2RS3
CH2RS2
CH2RS1
CH2RS0
CH3WEN
CH3RS6
CH3RS5
CH3RS4
CH3RS3
CH3RS2
CH3RS1
CH3RS0
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Bits CHnRS6 to CHnRS0 specify transfer request
sources to each channel. DMARSRA bits are allocated
to channels 0 to 3.
When writing to the CHnRS6 to CHnRS0 bits for each
channel, simultaneously write 1 to the CHnWEN bit.
Clearing the CHnWEN bit to 0 will not change the values
in the CHnRS6 to CHnRS0 bits of each channel and
retain the previous values. The CHnWEN bit is write-
enabled, but it does not retain the written value and is
always read as 0.
CHnRS[6:0]
H'00: Unused or auto-request, TMU input capture
H'10: DREQ0*
H'11: DREQ1*
H'12: DREQ2*
H'13: DREQ3*
H'14: DMABRG (LCDC reception,
H'20: SCIF(0) Transmit-data-empty
H'21: SCIF(0) Receive-data-full
H'22: SCIF(1) Transmit-data-empty
H'23: SCIF(1) Receive-data-full
H'24: SCIF(2) Transmit-data-empty
H'25: SCIF(2) Receive-data-full
H'26: HSPI Transmit data
H'27: HSPI Receive data
H'28: SIM Transmit data empty
H'29: SIM Receive-data-full
H'2B: MMC FIFO ready
H'2C: ADC AD conversion end data transfer
H'2D: Setting prohibited
H'2E: Setting prohibited
H'7F: --*
Other than above: Setting prohibited
interrupt
USB transmission/reception,
HAC transmission/reception,
SSI transmission/reception)*
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Rev. 2.00 Feb. 12, 2010 Page 403 of 1330
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REJ09B0554-0200