HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 56

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 29 A/D Converter (ADC) ...................................................................1039
29.1 Features............................................................................................................................ 1039
29.2 Input/Output Pins ............................................................................................................. 1041
29.3 Register Descriptions ....................................................................................................... 1042
29.4 Operation ......................................................................................................................... 1047
29.5 Interrupts.......................................................................................................................... 1056
29.6 Definitions of A/D Conversion Accuracy........................................................................ 1056
29.7 Usage Notes ..................................................................................................................... 1057
Section 30 LCD Controller (LCDC) ...............................................................1063
30.1 Features............................................................................................................................ 1063
30.2 Input/Output Pins ............................................................................................................. 1064
30.3 Register Configuration..................................................................................................... 1065
Rev. 2.00 Feb. 12, 2010 Page liv of lxxxii
REJ09B0554-0200
29.3.1 A/D Conversion Data Registers A to D (ADDRA to ADDRD) ......................... 1043
29.3.2 A/D Control/Status Register (ADCSR) .............................................................. 1044
29.4.1 Single Mode........................................................................................................ 1047
29.4.2 Multi Mode ......................................................................................................... 1049
29.4.3 Scan Mode .......................................................................................................... 1051
29.4.4 A/D Conversion Time......................................................................................... 1054
29.4.5 External Trigger Input Timing............................................................................ 1055
29.7.1 Setting Analog Input Voltage ............................................................................. 1057
29.7.2 Processing of Analog Input Pins......................................................................... 1058
29.7.3 Pck and Clock Division Ratio Settings ............................................................... 1059
29.7.4 Notes on Standby Modes .................................................................................... 1059
29.7.5 Notice of the DMA transmission of A/D converter ............................................ 1059
29.7.6 Notice of Scan mode and Multi mode of A/D conversion .................................. 1060
29.7.7 Notice of Multi mode of A/D conversion ........................................................... 1061
30.3.1 LCDC Input Clock Register (LDICKR) ............................................................. 1068
30.3.2 LCDC Module Type Register (LDMTR) ........................................................... 1069
30.3.3 LCDC Data Format Register (LDDFR) .............................................................. 1072
30.3.4 LCDC Scan Mode Register (LDSMR) ............................................................... 1074
30.3.5 LCDC Display Start Address Register - Upper (LDSARU) ............................... 1075
30.3.6 LCDC Display Start Address Register – Lower (LDSARL) .............................. 1076
30.3.7 LCDC Display Line Address Offset Register (LDLAOR) ................................. 1077
30.3.8 LCDC Palette Control Register (LDPALCR)..................................................... 1078
30.3.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ..................................... 1079
30.3.10 LCDC Horizontal Character Number Register (LDHCNR) ............................... 1080
30.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR) ....................................... 1081
30.3.12 LCDC Vertical Display Line Number Register (LDVDLNR) ........................... 1082
30.3.13 LCDC Vertical Total Line Number Register (LDVTLNR)................................ 1083
30.3.14 LCDC Vertical Sync Signal Register (LDVSYNR) ........................................... 1084
30.3.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) ..... 1085