HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 951

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

24.1
The PFC has the following features.
• Individual control of pull-up of each port pin used by a peripheral module
• Individual control of high-impedance (Hi-Z) state of pins used by the SCIF in software standby
• Applicable modules are selectable by the MFI mode/LCD mode
This LSI has ten general ports (A to H, J, and K), which provide 69 input/output pins and one
output pin in total.
The GPIO (general port for input/output) has the following features.
• Each port pin is multiplexed pin, for which the port control register can set the pin function and
• Each port has a data register that stores data for the pins.
• GPIO interrupts are supported.
For details of multiplexed pins, refer to table 24.1, Multiplexed Pins Controlled by Port Control
Registers. For pin multiplexing in this LSI, refer to table 1.3 and 1.4. By default, each pin of the
ports is pulled up.
Table 24.1 Multiplexed Pins Controlled by Port Control Registers
Pin Name
CAN0_NERR/AUDCK*
CAN0_RX/AUDATA[2]*
CAN0_TX/AUDATA[0]*
CAN1_NERR/AUDSYNC*
CAN1_RX/AUDATA[3]*
CAN1_TX/AUDATA[1]*
SSI0_SCK/HAC_SD_IN0/BS2*
SSI0_WS/HAC_SYNC0*
SSI0_SDATA/HAC_SD_OUT0*
mode
pull-up MOS control individually.
Features
Section 24 Pin Function Controller (PFC)
1
1
1
1
1
1
1
1
1
*
2
Port
A
A
A
A
A
A
B
B
B
GPIO
PTA7 input/output
PTA6 input/output
PTA5 input/output
PTA4 input/output
PTA3 input/output
PTA2 input/output
PTB7 input/output
PTB6 input/output
PTB5 input/output
MFI Mode
(MD7=0)
Rev. 2.00 Feb. 12, 2010 Page 867 of 1330
HCAN2[0]/AUD
HCAN2[0]/AUD
HCAN2[0]/AUD
HCAN2[1]/AUD
HCAN2[1]/AUD
HCAN2[1]/AUD
SSI[0]/HAC[0]
SSI[0]/HAC[0]
SSI[0]/HAC[0]
LCD Mode
(MD7 = 1)
REJ09B0554-0200
Register
Setting
AUD
AUD
AUD
AUD
AUD
AUD
BS2