HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 561

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(1) 8-Bit Data Transfer for SSI
When SSI handles the transfer of 8-bit (byte) audio data, data transfer starts from the least-
significant byte as shown in figure 11.36: first the left channel data is input to or output from bits 7
to 0, secondly the right channel data is input to or output from bits 15 to 8, and then the next left
channel data is input to or output from bits 23 to 16. Selecting big endian mode (MD5 = 0)
requires the conversion for alignment such that the least-significant byte is stored in the highest
address in the transmit/receive buffer in synchronous DRAM
(DMAACR.TAM[1:0]/DMAACR.RAM[1:0] = 01).
(2) 16-Bit Data Transfer for HAC/SSI
When HAC or SSI handles the transfer of 16-bit (word) audio data, data transfer starts from the
least-significant word as shown in figure 11.37: first the left channel data is input to or output
from bits 15 to 0 and then the right channel data is input to or output from bits 31 to 16. Selecting
big endian mode (MD5 = 0) requires the conversion for alignment such that the least-significant
word is stored in the highest address in a transmit/receive buffer in synchronous DRAM
(DMAACR.TAM[1:0]/DMAACR.RAM[1:0] = 10).
Slot data
Transfer data
External bus
Address on memory side
TAM[1:0]/RAM[1:0] = 01
TAM[1:0]/RAM[1:0] = 00
Slot data
Transfer data
External bus
Address on memory side
TAM[1:0]/RAM[1:0] = 01
TAM[1:0]/RAM[1:0] = 00
Big endian (conversion needed)
Big endian (conversion needed)
31-24
31-24
31-24
31-24
Figure 11.37 16-Bit Data Transfer for HAC/SSI
R1
+0
L0
+0
Figure 11.36 8-Bit Data Transfer for SSI
R
L
23-16
23-16
23-16
23-16
R0
L1
+1
15-8
15-8
15-8
15-8
R0
+2
L1
+2
R
L
7-0
7-0
7-0
7-0
R1
L0
+3
Slot data
Transfer data
External bus
Address on memory side
TTAM[1:0]/RAM[1:0] = 01
TAM[1:0]/RAM[1:0] = 00
Slot data
Transfer data
External bus
Address on memory side
TAM[1:0]/RAM[1:0] = 01
TAM[1:0]/RAM[1:0] = 00
Rev. 2.00 Feb. 12, 2010 Page 477 of 1330
Little endian (conversion not needed)
Little endian (conversion not needed)
31-24
31-24
31-24
31-24
R1
R1
+3
+2
R
R
23-16
23-16
23-16
23-16
L1
+2
L1
REJ09B0554-0200
15-8
15-8
15-8
15-8
R0
R0
+1
+0
L
L
7-0
7-0
7-0
7-0
L0
+0
L0