HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1206

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Break address register A
Break ASID register A
Break address mask register A BAMRA
Break bus cycle register A
Break address register B
Break ASID register B
Break address mask register B BAMRB
Break bus cycle register B
Break data register B
Break data mask register B
Break control register
Table 31.1 Register Configuration (2)
Register Name
Notes: 1. This value includes an undefined bit value. Refer to the register description.
The access size must be the same as the control register size. If the access size is different from the
register size, no data will be written to the register and an undefined value will be read.
UBC control register contents cannot be transferred to a floating-point register using a floating-
point memory data transfer instruction. When a UBC control register is updated, use either of the
following methods to make the updated value valid:
1. Execute an RTE instruction after the memory store instruction that updated the register. The
2. Execute instructions requiring 5 states for execution after the memory store instruction that
Rev. 2.00 Feb. 12, 2010 Page 1122 of 1330
REJ09B0554-0200
updated value will be valid from the RTE instruction destination onward.
updated the register. This LSI executes two instructions in parallel and a minimum of 0.5 states
are required for execution of one instruction, 11 instructions must be inserted. The updated
value will be valid from the 6th state onward.
2. After exiting hardware standby mode, this LSI enters the power-on reset state caused
by the RESET pin.
BARA
BASRA
BBRA
BARB
BASRB
BBRB
BDRB
BDMRB
BRCR
Abbrev.
Undefined
Undefined
Undefined
H'0000
Undefined
Undefined
Undefined
H'0000
Undefined
Undefined
H'0000*
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
1
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Manual Reset
by RESET
Pin/WDT/
Multiple
Exception
Sleep
by Sleep
Instruction/
Deep Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
by Hardware
*
2
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
by Software/
Each Module