HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1005

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Notes: 1. CMDAMT and CMDDMT have no associated interrupts. Poll these bits until they are
25.3.8
HACRIER is a 32-bit read/write register that enables or disables HAC RX interrupts.
Initial value:
Initial value:
Bit
9
8
7 to 0
Bit
31 to 23 ⎯
22
R/W:
R/W:
Bit:
Bit:
2. These bits are read/write. Writing 0 to the bit initializes it but writing 1 has no effect.
Bit Name
PLTFUN
PRTFUN
⎯
RX Interrupt Enable Register (HACRIER)
Bit Name
STARYIE
read as 1 before writing a new command to HACCSAR/HACCSDR. When bit 19 (RW)
of HACCSAR is 0 and TX12_ATOMIC is 1, take the following steps:
31
15
1. Initialize CMDDMT and CMDAMT before first accessing a codec register after HAC
2. After making the settings in HACCSDR and HACCSAR, poll CMDDMT and
3. Now the next write to a register is available.
-
R
R
0
-
0
initialization by any reset event.
CMDAMT until they are cleared to 1, and then initialize these bits.
30
14
R
R
0
-
0
-
PLRF
OVIE
R/W
29
13
R
0
0
-
Initial Value
0
0
All 0
Initial Value
All 0
0
PRRF
OVIE
R/W
28
12
R
0
0
-
27
11
R
R
0
-
0
-
R/W*
R/W
R/W
R
26
10
R
R
0
0
-
-
R/W
R
R/W
2
25
R
R
-
0
9
0
-
Description
PCML TX Underrun
0: No PCML TX underrun has occurred.
1: PCML TX underrun has occurred because the
PCMR TX Underrun
0: No PCMR TX underrun has occurred.
1: PCMR TX underrun has occurred because the
Reserved
Always 0 for read and write.
Description
Reserved
Always 0 for read and write.
Status Address Ready Interrupt Enable
0: Disables status address ready interrupts.
1: Enables status address ready interrupts.
24
R
R
0
8
0
-
-
codec has requested slot 3 with PLTFRQ = 1.
codec has requested slot 4 with PRTFRQ = 1.
23
R
R
0
0
7
-
-
Rev. 2.00 Feb. 12, 2010 Page 921 of 1330
STAR
R/W
YIE
22
R
0
6
0
-
STDR
R/W
YIE
21
R
0
5
0
-
PLRF
RQIE
R/W
20
R
0
4
0
-
PRRF
RQIE
R/W
19
R
0
3
0
-
REJ09B0554-0200
18
R
R
0
2
0
-
-
17
R
R
0
1
-
0
-
16
R
R
0
0
0
-
-