HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 259

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The following two kinds of operation can be used on the IC data array:
1. IC data array read
2. IC data array write
7.6.3
The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification. The way and entry to be accessed are specified in the address field,
and the write tag, U bit, and V bit are specified in the data field.
In the address field, bits [31:24] have the value H'F4 indicating the OC address array, the way is
specified by bit [14], and the entry by bits [13:5]. The OIX bit in CCR has no effect on this entry
specification. In RAM mode (ORA = 1 in CCR), the OC address arrays are only accessible in the
memory-mapped cache area, and bit [13] is used to specify the way. For details about address
mapping, see section 7.6.5, Summary of Memory-Mapping of OC. The association bit (A bit) [3]
in the address field specifies whether or not association is performed when writing to the OC
address array. As only longword access is used, 0 should be specified for address field bits [1:0].
In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0].
As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a
write in which association is not performed. Data field bits [31:29] are used for the virtual address
specification only in the case of a write in which association is performed.
Longword data is read into the data field from the data specified by the longword specification
bits in the address field in the IC entry corresponding to the way and entry set in the address
field.
The longword data specified in the data field is written for the data specified by the longword
specification bits in the address field in the IC entry corresponding to the way and entry set in
the address field.
OC Address Array
Address field
Data field
31
31
L
1 1 1 1 0 0 0 1
: Longword specification bits
: Reserved bits (write value should be 0, and read value is undefined )
Figure 7.10 Memory-Mapped IC Data Array
24
23
Longword data
14
Way
13
Rev. 2.00 Feb. 12, 2010 Page 175 of 1330
12
Entry
5 4
L
2 1 0
REJ09B0554-0200
0