HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 41

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.6
Section 7 Caches ...............................................................................................151
7.1
7.2
7.3
7.4
7.5
7.6
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
Memory-Mapped TLB Configuration.............................................................................. 143
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
Features ............................................................................................................................ 151
Register Descriptions ....................................................................................................... 155
7.2.1
7.2.2
7.2.3
Operand Cache Operation ................................................................................................ 159
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
Instruction Cache Operation ............................................................................................ 167
7.4.1
7.4.2
Memory-Mapped Cache Configuration (Cache Direct Mapping Mode) ......................... 168
7.5.1
7.5.2
7.5.3
7.5.4
Memory-Mapped Cache Configuration (Double-Size Cache Mode)............................... 173
7.6.1
7.6.2
Instruction TLB Multiple Hit Exception............................................................. 137
Instruction TLB Miss Exception......................................................................... 137
Instruction TLB Protection Violation Exception ................................................ 138
Data TLB Multiple Hit Exception....................................................................... 139
Data TLB Miss Exception................................................................................... 140
Data TLB Protection Violation Exception .......................................................... 141
Initial Page Write Exception ............................................................................... 142
ITLB Address Array ........................................................................................... 143
ITLB Data Array 1.............................................................................................. 144
ITLB Data Array 2.............................................................................................. 145
UTLB Address Array.......................................................................................... 146
UTLB Data Array 1 ............................................................................................ 147
UTLB Data Array 2 ............................................................................................ 148
Cache Control Register (CCR) ........................................................................... 156
Queue Address Control Register 0 (QACR0) ..................................................... 158
Queue Address Control Register 1 (QACR1) ..................................................... 159
Read Operation ................................................................................................... 159
Write Operation .................................................................................................. 160
Write-Back Buffer .............................................................................................. 162
Write-Through Buffer ......................................................................................... 162
RAM Mode ......................................................................................................... 162
OC Index Mode................................................................................................... 163
Coherency between Cache and External Memory .............................................. 163
Prefetch Operation .............................................................................................. 164
Note on Using Cache Enhanced Mode ............................................................... 164
Read Operation ................................................................................................... 167
IC Index Mode .................................................................................................... 167
IC Address Array ................................................................................................ 168
IC Data Array...................................................................................................... 169
OC Address Array............................................................................................... 170
OC Data Array .................................................................................................... 172
IC Address Array ................................................................................................ 173
IC Data Array...................................................................................................... 174
Rev. 2.00 Feb. 12, 2010 Page xxxix of lxxxii
REJ09B0554-0200