HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1135

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

29.4.3
In scan mode, analog inputs for a maximum of four specified channels are converted in succession
as shown below.
1. When the ADST bit in ADCSR is set to 1 by software or an external trigger input, A/D
2. A/D conversion for the first channel starts. When multiple channels are selected, the input
3. When conversion of each channel ends, the conversion results are transmitted to the ADDRA
4. When conversion of all selected channel ends, the ADF bit of ADCSR is set to 1. If the ADIE
5.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described
below. Figure 29.4 shows a timing diagram for this example.
1. Select scan mode as the operating mode (MDS1 = 1 and MDS0 = 1) and AN0 to AN2 as the
2. A/D conversion of the first channel (AN0) starts. When the A/D conversion ends, the result is
3. Conversion proceeds in the same way up to the third channel (AN2).
4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF bit is set to 1,
5. While the ADST bit is set to 1, steps 2 to 4 above are repeated. When the ADST bit is cleared
conversion starts with the first channel (AN0).
signal for the second channel (AN1) is converted after the A/D conversion for the first channel
ends.
to ADDRD data register that corresponds to the channel.
bit is also set to 1, an ADI interrupt is generated at this time.
input channels (CH1 = 1 and CH0 = 0). Then start A/D conversion (ADST = 1).
transferred into ADDRA. Next, the second channel (AN1) is selected automatically and A/D
conversion starts.
the first channel (AN0) is selected again, and A/D conversion is consecutively performed. (In
multi mode, A/D conversion ends when the selected channels have been cycled through.
However, in scan mode, after the selected channels have been cycled through, A/D conversion
starts again from the first channel and is consecutively repeated.)
If the DMASL bit is cleared to 0 and the ADIE bit is set to 1 at this time, an ADI interrupt is
generated after A/D conversion ends.
to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again
from the first channel (AN0).
While the ADST bit is set to 1, it is not automatically cleared, but steps 2 to 4 above are
repeated. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter
becomes idle.
Scan Mode
Rev. 2.00 Feb. 12, 2010 Page 1051 of 1330
REJ09B0554-0200