HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 625

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

15.4
Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR).
Each TCNT performs count-down operation. The channels have an auto-reload function that
allows cyclic count operations, and can also perform external event counting. Channel 2 also has
an input capture function.
15.4.1
When one of bits STR0 to STR2 in TSTR is set to 1, the TCNT for the corresponding channel
starts counting. When TCNT underflows, the UNF flag in TCR is set. If the UNIE bit in TCR is
set to 1 at this time, an interrupt request is sent to the CPU. At the same time, the value is copied
from TCOR into TCNT, and the count-down continues (auto-reload function).
(1) Example of Count Operation Setting Procedure
Figure 15.2 shows an example of the count operation setting procedure.
Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt
Operation
Counter Operation
Underflow interrupt
Select count clock
generation setting
Select operation
Timer constant
register setting
Set initial timer
counter value
Start count
enabled state is set without clearing the flag, another interrupt will be generated.
Figure 15.2 Example of Count Operation Setting Procedure
Input capture interrupt
generation setting
(1)
(2)
(4)
(5)
(6)
When input capture
function is used
(3)
(1)
(2)
(3)
(4)
(5)
(6)
Select the count clock with the TPSC2 to TPSC0
bits in TCR. When the external clock (TCLK) is
selected, specify the external clock edge with the
CKEG1 and CKEG0 bits in TCR.
Specify whether an interrupt is to be generated
on TCNT underflow with the UNIE bit in TCR.
When the input capture function is used, set the
ICPE bits in TCR, including specification of
whether the interrupt function is to be used.
Set a value in TCOR.
Set the initial value inTCNT.
Set the STR bit to 1 in TSTR to start the count.
Rev. 2.00 Feb. 12, 2010 Page 541 of 1330
REJ09B0554-0200