HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 739

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(4) Switching modes
When switching from receiver mode to transmitter mode, after confirming that reception has been
completed, and then set RE = 0 and TE = 1. Completion of reception can be confirmed through the
RDRF flag.
When switching from transmitter mode to receiver mode, after confirming that transmission has
been completed, and then set TE = 0 and RE = 1. Completion of transmission can be confirmed
through the TDRE and TEND flags.
(5) Interrupt operations
The smart card interface has four types of interrupt sources: transmit data empty interrupt
(SIMTXI) requests, transmit/receive error interrupt (SIMERI) requests, receive data full interrupt
(SIMRXI) requests, and transmission end interrupt (SIMTEI) requests.
Table 18.5 describes the interrupt sources for the smart card interface. Each of the interrupt
requests can be enabled or disabled using the TIE, RIE, TEIE, and WAIT_IE bits in SISCR and
the EIO bit in SISC2R. In addition, each interrupt request can be sent independently to the
interrupt controller.
Table 18.5 Smart Card Interface Interrupt Sources
(6) Data transfer using DMAC
The smart card interface enables reception and transmission in T=0 and T=1 modes using DMAC.
In transmission, when the TDRE flag in SISSR is set to 1, a transmit data empty DMA transfer
request is issued. If a transmit data empty DMA transfer request is set in advance as a DMAC
startup factor, the DMAC can be started and made to transfer data when a transmit data empty
DMA transfer request occurs.
Operating State
Transmitter mode
Receiver mode
Normal operation
Error
Normal operation
Error
ERS
RDRF
ORER, PER
Flags
TDRE
TEND
WAIT_ER
Rev. 2.00 Feb. 12, 2010 Page 655 of 1330
Mask Bits
TIE
TEIE
RIE
RIE, EIO
RIE
WAIT_IE
Interrupt Sources
SIMTXI
SIMTEI
SIMERI
SIMRXI
SIMERI
SIMERI
REJ09B0554-0200