HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 409

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(5) Burst Write
The timing chart for a burst write is shown in figure 10.18. In this LSI, a burst write occurs only in
the event of 32-byte transfer. In a burst write operation, the WRIT command is issued in cycle Tc1
following the Tr cycle where the ACTV command is output, and then 4 cycles later, the WRITA
command is issued. In the write cycle, the write data is output at the same time as the write
command. For the write with auto-precharge command, precharging of the relevant bank is
performed in the synchronous DRAM after completion of the write command, and therefore no
command can be issued for the same bank until precharging is completed. Consequently, in
addition to the precharge wait cycle Tpc used in a read access, cycle Trwl is also added as a wait
cycle until precharging is started following the write command for delaying issuance of a new
command for the synchronous DRAM during this period. Bits TRWL2 to TRWL0 in MCR can be
used to specify the number of Trwl cycles. Access is started from 16-byte boundary data, and 32-
byte boundary data is written in wraparound mode. DACK is asserted two cycles before the data
write cycle.
Bank
Address
D31–D0
(write)
DACKn
(SA: IO → memory)
CKIO
Precharge-sel
CSn
RD/WR
RAS
CASS
DQMn
BS
CKE
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.18 Basic Timing for Synchronous DRAM Burst Write
Tr
Row
Row
Row
Trw
Tc1
c1
Tc2
c2
H/L
c1
Tc3
c3
Tc4
c4
Tc5
c5
Tc6
Rev. 2.00 Feb. 12, 2010 Page 325 of 1330
c6
H/L
c5
Tc7
c7
Tc8
c8
Trw1
REJ09B0554-0200
Trw1
Tpc