HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1058

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(5) Commands with Read Data
Flash memory operation commands include a number of commands involving read data. Such
commands confirm the card status by the command argument and command response, and receive
card information and flash memory data from the MCDAT pin.
The number of bytes of the flash memory to be read is specified by CMD16 as a block size, or if
not specified, reading is continued until it is aborted by CMD12 during multiblock or stream
transfer. In multiblock transfer, the transfer operation is suspended for every block and an
instruction to continue or end the command sequence is waited for.
Whether the command sequence is suspended or not during the sequence depends on the size of
the block and FIFO. The command sequence ends without suspending the data transfer when
block size ≤ FIFO size. When block size > FIFO size, the command sequence is suspended by
FIFO full. Once the command sequence is suspended, data in FIFO is processed before the
command sequence is continued. In multiblock transfer, the command sequence is suspended for
every block.
In multiblock transfer, when a block size is set to 4 or 8 bytes and the CMDOFF bit of OPCR is
set to 1 for only one block, the command response may not be received correctly. Therefore, when
a block size is set to 4 or 8 bytes, the command sequence must be completed after reading at least
two blocks.
Figures 26.8 to 26.11 show examples of the command sequence for commands with read data.
Figures 26.12 to 26.14 show the operational flows for commands with read data.
• Make settings to issue the command, and clear FIFO.
• Set the START bit in CMDSTRT to 1 to start command transmission. MCCMD must be kept
• The command response is received from the card.
• Read data is received from the card.
• The inter-block suspension in multiblock transfer and suspension by the FIFO full are detected
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driven until the end bit output is completed.
Command transmission completion can be confirmed by the command transmit end interrupt
(CMDI).
If the card does not return the command response, the command response is detected by the
command timeout error (CTERI).
by the data transfer end interrupt (DTI) and FIFO full interrupt (FFI), respectively.
To continue the command sequence, the RD_CONTI bit in OPCR should be set to 1. To end
the command sequence, the CMDOFF bit in OPCR should be set to 1, and the CMD12 should
be issued.