HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 74

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 33.38 Synchronous DRAM Bus Cycle: Mode Register Setting (PALL) ....................... 1261
Figure 33.39 Synchronous DRAM Bus Cycle: Mode Register Setting (SET) .......................... 1262
Figure 33.40 PCMCIA Memory Bus Cycle .............................................................................. 1263
Figure 33.41 PCMCIA I/O Bus Cycle....................................................................................... 1264
Figure 33.42 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Internal Wait, Bus Sizing) ... 1265
Figure 33.43 MPX Basic Bus Cycle: Read................................................................................ 1266
Figure 33.44 MPX Basic Bus Cycle: Write............................................................................... 1267
Figure 33.45 MPX Bus Cycle: Burst Read................................................................................ 1268
Figure 33.46 MPX Bus Cycle: Burst Write............................................................................... 1269
Figure 33.47 Memory Byte Control SRAM Bus Cycle............................................................. 1270
Figure 33.48 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address
Figure 33.49 NMI Input Timing................................................................................................ 1272
Figure 33.50 DREQ/DRAK Timing.......................................................................................... 1273
Figure 33.51 TCLK Input Timing ............................................................................................. 1273
Figure 33.52 SCIFn_CLK Input Clock Timing......................................................................... 1274
Figure 33.53 SCIF I/O Synchronous Mode Clock Timing........................................................ 1274
Figure 33.54 TCK Input Timing................................................................................................ 1275
Figure 33.55 RESET Hold Timing............................................................................................ 1275
Figure 33.56 H-UDI Data Transfer Timing............................................................................... 1276
Figure 33.57 Pin Break Timing ................................................................................................. 1276
Figure 33.58 CMT Timing (1)................................................................................................... 1276
Figure 33.59 CMT Timing (2)................................................................................................... 1277
Figure 33.60 HCAN2 Timing.................................................................................................... 1277
Figure 33.61 GPIO Timing........................................................................................................ 1278
Figure 33.62 Block Diagram of I
Figure 33.63 I
Figure 33.64 HSPI Data Output/Input Timing .......................................................................... 1283
Figure 33.65 Input Voltage (V
Figure 33.66 Output (V
Figure 33.67 Differential Input Sensitivity (VDI), Differential common mode range
Figure 33.68 Load Condition of AC Characteristics (Full speed) ............................................. 1285
Figure 33.69 Load Condition of AC Characteristics (Low speed) ............................................ 1286
Figure 33.70 t
Figure 33.71 V
Figure 33.72 AC Characteristics of 68 Series Bus .................................................................... 1288
Figure 33.73 AC Characteristics of 80 Series Bus (Read)......................................................... 1289
Figure 33.74 AC Characteristics of 80 Series Bus (Write)........................................................ 1289
Figure 33.75 SIM Module Signal Timing ................................................................................. 1290
Figure 33.76 MMCIF Transmit Timing .................................................................................... 1291
Figure 33.77 MMCIF Receive Timing ...................................................................................... 1291
Rev. 2.00 Feb. 12, 2010 Page lxxii of lxxxii
REJ09B0554-0200
Setup/Hold Time Insertion, AnS = 1, AnH = 1)................................................... 1271
(VCM) .................................................................................................................. 1284
r
2
, t
C Bus Interface Module Signal Timing ............................................................. 1281
CRS
f
........................................................................................................................ 1286
....................................................................................................................... 1286
OH
, V
OL
).................................................................................................. 1284
IH
, V
2
C I/O Buffer ......................................................................... 1279
IL
) ........................................................................................ 1284