HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 146

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• Matrix (4 × 4) × matrix (4 × 4):
Since approximate-value computations are performed to enable high-speed computation, the
inexact exception (I) bit in both the FPU exception cause field and flag field are always set to 1
when an FTRV instruction is executed. Therefore, if the I bit is set in the FPU exception enable
field, FPU exception handling will be executed. It is not possible to check all data types in the
registers beforehand when executing an FTRV instruction. If the V bit is set in the FPU exception
enable field, FPU exception handling will be executed.
FRCHG: This instruction modifies banked registers. For example, when the FTRV instruction is
executed, matrix elements must be set in an array in the background bank. However, to create the
actual elements of a translation matrix, it is easier to use registers in the foreground bank. When
the LDS instruction is used on FPSCR, this instruction takes four to five cycles in order to
maintain the FPU state. With the FRCHG instruction, the FR bit in FPSCR can be changed in one
cycle.
3.6.2
In addition to the powerful new geometric operation instructions, the FPU also supports high-
speed data transfer instructions.
When the SZ bit is 1, the FPU can perform data transfer by means of pair single-precision data
transfer instructions.
• FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14)
• FMOV DRm/XDm, @Rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15)
These instructions enable two single-precision (2 × 32-bit) data items to be transferred; that is, the
transfer performance of these instructions is doubled.
• FSCHG
This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between use
and non-use of pair single-precision data transfer.
Programming Note: When the SZ bit is 1 and big-endian mode is used, FMOV can be used for a
double-precision floating-point load or store. In little-endian mode, a double-precision floating-
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This operation is generally used for viewpoint changes, angle changes, or movements called
vector transformations (4-dimensional). Since affine transformation processing for angle +
parallel movement basically requires a 4 × 4 matrix, the FPU supports 4-dimensional
operations.
This operation requires the execution of four FTRV instructions.
Pair Single-Precision Data Transfer