HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 389

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 Bus State Controller (BSC)
10.6.2
Areas
(1) Area 0
For area 0, off-chip address bits A28 to A26 are 000.
The interfaces that can be set for this area are SRAM, MPX, and burst ROM.
A bus width of 8, 16, or 32 bits is selectable with pins MD4 and MD3 at a power-on reset caused
by the RESET pin.
When area 0 is accessed, the CS0 signal is asserted. In addition, the RD signal, which can be used
as OE, and write control signals WE0 to WE3 are asserted.
As regards the number of bus cycles, 0 to 15 wait cycles can be selected with bits A0W2 to A0W0
in WCR2. In addition, any number of wait cycles can be inserted in each bus cycle by the external
wait pin (RDY).
When the burst ROM interface is in use, the number of bus cycles for burst transfer is selected in
the range of 2 to 9 according to the number of wait cycles.
The setup time of the address and CS signal with respect to the read/write strobe can be specified
by bit A0S0 in WCR3 within a range of 0 to 1 cycle. The data-hold time of the address and CS
signal with respect to the read/write strobe can be specified by bits A0H1 and A0H0 within a
range of 0 to 3 cycles.
(2) Area 1
For area 1, off-chip address bits A28 to A26 are 001.
The interfaces that can be set for this area are SRAM, MPX, and byte control SRAM.
When the SRAM interface is in use, a bus width of 8, 16, or 32 bits is selectable with bits A1SZ1
and A1SZ0 in BCR2. When the MPX interface is in use, a bus width of 32 bits should be selected
by bits A1SZ1 and A1SZ0 in BCR2. When the byte control SRAM interface is in use, select a bus
width of 16 or 32 bits.
When area 1 is accessed, the CS1 signal is asserted. In addition, the RD signal, which can be used
as OE, and write control signals WE0 to WE3 are asserted.
As regards the number of bus cycles, 0 to 15 wait cycles is selectable with bits A1W2 to A1W0 in
WCR2. In addition, any number of wait cycles can be inserted in each bus cycle by the external
wait pin (RDY).
Rev. 2.00 Feb. 12, 2010 Page 305 of 1330
REJ09B0554-0200