HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 760

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 I
Note: * This bit can be written or read. When 0 is written to, the bit is initialized. When 1 is written
Rev. 2.00 Feb. 12, 2010 Page 676 of 1330
REJ09B0554-0200
Bit
3
2
1
0
to, it is ignored.
Bit Name
MDE
MDT
MDR
MAT
2
C Bus Interface
Initial Value
0
0
0
0
R/W
R/W*
R/W*
R/W*
R/W*
Description
Master Data Empty
At the start of a byte-data transmission, the
contents of the transmit data register are loaded
to a shift register, which is ready for passing data
onto the bus.
MDE = 1 indicates that this load operation has
taken place and the transmit data register is ready
to receive further data.
In the master transmit mode, the MDE and MAT
bits are simultaneously set to 1 after the slave
address has been sent. In this case, clear the
MDE and MAT bits to 0 after clearing the ESG bit
of the ICMCR to 0. The data transmission is then
resumed.
Master Data Transmission
The master has transmitted a byte of data to the
slave on the bus. This status bit becomes 1 after
the falling edge of SCL during the last data bit
transmission.
Master Data Reception
The master has received a byte of data from the
bus and the receive data register is ready. This
status bit becomes active after the falling edge of
SCL during the last data bit reception. In the
single buffer mode, this status bit must be reset
after data has been read from the receive data
register. In the FIFO buffer mode, this bit is not
used.
When MDBS = 1, SCL is held low from the
moment the receive data register starts receiving
data packets until the MDR bit is cleared to 0.
In the master receive mode, the MDE and MAT
bits are simultaneously set to 1 after the slave
address has been sent. In this case, clear the
MDE and MAT bits to 0 after clearing the ESG bit
of the ICMCR to 0. The data transmission is then
resumed.
Master Address Transmission
The master has transmitted the slave address
byte of a data packet. This bit becomes 1 after the
falling edge of SCL during the output of the ack bit
which is sent after an address.