HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 429

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 Bus State Controller (BSC)
10.6.5
Burst ROM Interface
Setting bits A0BST2 to A0BST0, A5BST2 to A5BST0, and A6BST2 to A6BST0 in BCR1 to a
non-zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface
provides high-speed access to ROM that has a burst access function. The timing for burst access to
burst ROM is shown in figure 10.33. No wait cycle is set. Basically, access is performed in the
same way as for SRAM interface, but when the first cycle ends, only the address is changed, and
then the next access is executed. When ROM having an 8-bit data width is connected, bits
A0BST2 to A0BST0, A5BST2 to A5BST0, or A6BST2 to A6BST0 can be used to set the number
of consecutive accesses to 4, 8, 16, or 32. When ROM having a 16-bit data width is connected, 4,
8, or 16 accesses can be set in the same way. When ROM having a 32-bit data width is connected,
4 or 8 accesses can be set.
The RDY pin sampling is always performed when one or more wait cycles are set. The timing in
this case is shown in figure 10.34.
The second and subsequent access cycles also comprise two cycles when a burst ROM setting is
made and the wait is specified at 0.
The write operation for a burst ROM interface is performed as a SRAM interface.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the bus width that
was set. The first access is performed on the data where there was an access request, and the
remaining accesses are performed on the 32-byte boundary data. The bus is not released during
this operation.
Figure 10.35 shows the timing when the burst ROM is set and a setup/hold is specified by WCR3.
Rev. 2.00 Feb. 12, 2010 Page 345 of 1330
REJ09B0554-0200