HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 44

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.7 Usage Notes ..................................................................................................................... 378
Section 11 Direct Memory Access Controller (DMAC) .................................. 379
11.1 Features............................................................................................................................ 379
11.2 Input/Output Pins ............................................................................................................. 382
11.3 Register Descriptions ....................................................................................................... 383
11.4 Operation ......................................................................................................................... 424
11.5 Examples of Use .............................................................................................................. 465
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REJ09B0554-0200
10.6.7 MPX Interface..................................................................................................... 359
10.6.8 Byte Control SRAM Interface ............................................................................ 369
10.6.9 Waits between Access Cycles............................................................................. 374
10.6.10 Bus Arbitration ................................................................................................... 375
10.6.11 Bus Release and Acquire Sequences .................................................................. 377
10.7.1 Refresh ................................................................................................................ 378
10.7.2 Bus Arbitration ................................................................................................... 378
11.3.1 DMA Source Address Register (SAR) ............................................................... 388
11.3.2 DMA Destination Address Register (DAR) ....................................................... 389
11.3.3 DMA Transfer Count Register (DMATCR) ....................................................... 390
11.3.4 DMA Channel Control Register (CHCR) ........................................................... 391
11.3.5 DMA Operation Register (DMAOR) ................................................................. 400
11.3.6 DMA Request Resource Selection Registers (DMARSRA, DMARSRB) ......... 402
11.3.7 DMA Pin Control Register (DMAPCR) ............................................................. 406
11.3.8 DMA Request Control Register (DMARCR) ..................................................... 406
11.3.9 DMA BRG Control Register (DMABRGCR) .................................................... 410
11.3.10 DMA Audio Source Address Register (DMAATXSAR) ................................... 413
11.3.11 DMA Audio Destination Address Register (DMAARXDAR) ........................... 414
11.3.12 DMA Audio Transmit Transfer Count Register (DMAATXTCR)..................... 414
11.3.13 DMA Audio Receive Transfer Count Register (DMAARXTCR) ...................... 415
11.3.14 DMA Audio Control Register (DMAACR)........................................................ 416
11.3.15 DMA Audio Transmit Transfer Counter (DMAATXTCNT) ............................. 419
11.3.16 DMA Audio Receive Transfer Counter (DMAARXTCNT) .............................. 420
11.3.17 DMA USB Source Address Register (DMAUSAR)........................................... 420
11.3.18 DMA USB Destination Address Register (DMAUDAR)................................... 421
11.3.19 DMA USB R/W Size Register (DMAURWSZ) ................................................. 422
11.3.20 DMA USB Control Register (DMAUCR) .......................................................... 423
11.4.1 DMA Transfer Procedure ................................................................................... 424
11.4.2 DMA Transfer Requests ..................................................................................... 426
11.4.3 Channel Priorities ............................................................................................... 428
11.4.4 Types of DMA Transfer...................................................................................... 431
11.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing .................................. 440
11.4.6 Ending DMA Transfer ........................................................................................ 461
11.4.7 Interrupt-Request Codes ..................................................................................... 464