HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 312

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 Feb. 12, 2010 Page 228 of 1330
REJ09B0554-0200
Bit
14
13 to 10 —
9
8
7
Bit Name
MAI
NMIB
NMIE
IRLM
Initial Value
0
All 0
0
0
0
R/W
R/W
—
R/W
R/W
R/W
Description
NMI Interrupt Mask
Specifies whether or not all interrupts are to be
masked while the NMI pin input level is low,
irrespective of the BL bit in SR of the CPU. NMI
interrupts are accepted in normal operation and in
sleep mode. In standby mode, all interrupts are
masked, and standby is not cleared, while the
NMI pin is low.
0: Interrupts enabled even while NMI pin is low
1: Interrupts disabled while NMI pin is low
Reserved
These bits are always read as 0.The write value
should always be 0.
NMI Block Mode
Specifies whether an NMI request is to be held
pending or detected immediately while the BL bit
in SR of the CPU is set to 1.
If interrupt requests are enabled while the BL bit
is 1, the previous exception information will be
lost, and so must be saved beforehand. This bit is
cleared automatically by NMI acceptance.
0: NMI interrupt requests held pending while the
1: NMI interrupt requests detected while the BL
NMI Edge Select
Specifies whether the falling or rising edge of the
interrupt request signal to the NMI pin is detected.
0: Interrupt request detected on falling edge of
1: Interrupt request detected on rising edge of
IRL Pin Mode
Specifies whether pins IRL3 to IRL0 are to be
used as level-encoded interrupt requests or as
four independent interrupt requests.
0: IRL pins used as level-encoded interrupt
1: IRL pins used as four independent interrupt
BL bit in SR is set to 1
bit in SR is set to 1
NMI input
NMI input
requests
requests (level-sensing IRQ mode)