HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 872

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(4) Timer
With the use of the Time Stamp field, the Timer module allows HCAN2 to record the time in
which the messages are transmitted and received.
The timer is a 16-bit free running counter that can be controlled by the host CPU. It provides one
16-bit Compare Match Register that holds a reference timer value. When the value of the free
running 16-bit timer matches the reference value hold in the compare match register, an interrupt
signal is generated.
The clock period of this Timer offers a wide selection derived from the system clock.
The timer has registers CANTCNTR, CANTCR, and CANTCMR.
(5) CAN Interface
The CAN interface supports the CAN Bus Data Link Controller specification described in CAN
Specification Version 2.0, Robert Bosch GmbH, 1991. This block fulfils all the functions of the
standard DLC as specified by the OSI 7 Layer Reference model. This functional entity also
provides the registers and logic specific to a given CAN bus, which includes the Receive Error
Counter, Transmit Error Counter, the Bit Configuration Registers and various useful test modes.
This block also contains functional entities to hold the data received and the data to be transmitted
for the CAN Data Link Controller.
22.3
Table 22.1 summarizes the pins of the HCAN2.
Table 22.1 Pin Configuration
Rev. 2.00 Feb. 12, 2010 Page 788 of 1330
REJ09B0554-0200
Pin Name
CAN0_RX
CAN0_TX
CAN0_NERR
CAN1_RX
CAN1_TX
CAN1_NERR
Input/Output Pins
I/O
Input
Output
Input
Input
Output
Input
Function
CAN bus receive signal of channel 0
CAN bus transmit signal of channel 0
CAN bus error of channel 0
CAN bus receive signal of channel 1
CAN bus transmit signal of channel 1
CAN bus error of channel 1