HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 578

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.4.1
FRQCR is a 16-bit readable/writable register that specifies use/non-use of clock output from the
CKIO pin, on/off control of PLL circuits 1 and 2, and the frequency division ratios of the CPU
clock, bus clock, and peripheral clock. FRQCR can only be accessed in words.
FRQCR is initialized only by a power-on reset via the RESET pin. The initial value of each bit is
determined by the clock operating mode.
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 494 of 1330
REJ09B0554-0200
Bit
15 to 12 —
11
10
9
R/W:
Bit:
Frequency Control Register (FRQCR)
Bit Name
CKOEN
PLL1EN
PLL2EN
15
R
0
-
14
R
-
0
13
R
0
-
Initial Value
All 0
1
1
1
12
R
0
-
CKO
R/W
EN
11
1
PLL1
R/W
EN
10
1
R/W
R
R/W
R/W
R/W
PLL2
R/W
EN
9
1
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Output Enable
Specifies whether a clock is output from the CKIO
pin or the CKIO pin is placed in the high-
impedance state. When the CKIO pin goes to the
high-impedance state, operation continues at the
operating frequency before this state was
entered. When the CKIO pin becomes high-
impedance, it is pulled up. Note that the CKIO pin
is not pulled up in hardware standby mode.
0: CKIO pin goes to high-impedance state
1: Clock is output from CKIO pin
PLL Circuit 1 Enable
Specifies whether PLL circuit 1 is on or off.
0: PLL circuit 1 is not used
1: PLL circuit 1 is used
PLL Circuit 2 Enable
Specifies whether PLL circuit 2 is on or off.
0: PLL circuit 2 is not used
1: PLL circuit 2 is used
R/W
IFC2
8
-
IFC1
R/W
7
-
R/W
IFC0 BFC2 BFC1 BFC0 PFC2 PFC1 PFC0
6
-
R/W
5
-
R/W
4
-
R/W
3
-
R/W
2
-
R/W
1
-
R/W
0
-