HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 407

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 Bus State Controller (BSC)
(4) Single Read
The timing chart for a single read is shown in figure 10.17. In this LSI, since synchronous DRAM
is set to burst read/burst write mode, read data continues to be output even after the required data
has been received. To prevent data collisions, after the required data is read in cycle Td1, dummy
read cycles Td2 to Td4 are performed, and this LSI waits for the end of the synchronous DRAM
operation.
There are 4 burst transfers during a read. In cache-through and other DMA read cycles, the BS
signal is asserted and data is latched only in cycle Td1 of cycles Td1 to Td4.
Such dummy cycles increase the memory access time and tend to reduce program execution speed
and DMA transfer speed. It is important both to avoid access to unnecessary cache-through areas
and to use a data structure that allows data to be placed at a 32-byte boundary for transfer in 32-
byte units when carrying out DMA transfer with synchronous DRAM specified as the source.
Rev. 2.00 Feb. 12, 2010 Page 323 of 1330
REJ09B0554-0200