HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 800

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
20.3.2
SSISR is configured by status flags that indicate the operating status of the SSI module and bits
that indicate the current channel number and word number.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 716 of 1330
REJ09B0554-0200
Bit
0
Bit
31 to 29 ⎯
28
R/W:
R/W:
Bit:
Bit:
Bit Name
EN
Status Register (SSISR)
Bit Name
DMRQ
31
15
R
R
-
-
-
-
30
14
-
-
R
-
-
R
29
13
R
R
-
-
-
-
Initial Value
0
Initial Value
0
DMRQ
28
12
R
R
0
-
-
R/W*
UIRQ
27
11
R
0
-
-
R/W*
R/W
OIRQ
R/W
R
R
R/W
26
10
0
R
-
-
IIRQ
25
1
R
9
-
-
R
Description
0: The SSI module is disabled
1: The SSI module is enabled
Description
Reserved
These bits are always read as an undefined
value. The write value should always be 0.
DMA Request Status Flag
This status flag allows the CPU to see the status
of the DMA request of SSI module.
TRMD = 0 (Receive Mode):
TRMD = 1 (Transmit Mode):
SSI Module Enable
DIRQ
24
R
R
0
8
-
-
If DMRQ = 1 then SSIRDR has unread data.
If SSIRDR is read then DMRQ = 0 until there
is new unread data.
If DMRQ = 1, SSITDR requests data to be
written to continue the transmission onto the
audio serial bus.
Once data is written to SSITDR then DMRQ =
0 until further transmit data is requested.
23
R
R
7
-
-
-
-
22
R
R
6
-
-
-
-
21
R
R
5
-
-
-
-
20
R
R
4
-
-
-
-
CHNO1
19
3
-
R
0
R
-
CHNO0
18
2
-
R
0
R
-
SWNO
17
R
R
-
1
1
-
IDST
16
0
-
1
R
R
-

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