HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 77

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 1 Overview
Table 1.1
Table 1.2
Table 1.3
Table 1.4
Table 1.5
Table 1.6
Section 2 Programming Model
Table 2.1
Section 3 Floating-Point Unit (FPU)
Table 3.1
Table 3.2
Table 3.3
Section 4 Instruction Set
Table 4.1
Table 4.2
Table 4.3
Table 4.4
Table 4.5
Table 4.6
Table 4.7
Table 4.8
Table 4.9
Table 4.10
Table 4.11
Table 4.12
Section 5 Pipelining
Table 5.1
Table 5.2
Table 5.3
Section 6 Memory Management Unit (MMU)
Table 6.1
Table 6.1
Features ..................................................................................................................2
Pin Configuration (BP-256F: 21 mm) ....................................................................13
Pin Configuration (BP-256B: 17 mm)....................................................................22
Pin Functions..........................................................................................................31
Pin Functions..........................................................................................................32
Pin Functions..........................................................................................................35
Initial Register Values ............................................................................................41
Floating-Point Number Formats and Parameters ...................................................52
Floating-Point Ranges ............................................................................................53
Bit Allocation for FPU Exception Handling ..........................................................58
Addressing Modes and Effective Addresses ..........................................................69
Notation Used in Instruction List ...........................................................................73
Fixed-Point Transfer Instructions...........................................................................74
Arithmetic Operation Instructions..........................................................................75
Logic Operation Instructions..................................................................................77
Shift Instructions ....................................................................................................78
Branch Instructions.................................................................................................79
System Control Instructions ...................................................................................80
Floating-Point Single-Precision Instructions..........................................................82
Floating-Point Double-Precision Instructions ........................................................83
Floating-Point Control Instructions ........................................................................83
Floating-Point Graphics Acceleration Instructions ................................................84
Instruction Groups..................................................................................................94
Parallel-Executability .............................................................................................97
Execution Cycles....................................................................................................104
Register Configuration (1)......................................................................................121
Register Configuration (2)......................................................................................122
Tables
Rev. 2.00 Feb. 12, 2010 Page lxxv of lxxxii
REJ09B0554-0200