HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 486

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.3.6
DMARSRA and DMARSRB are 32-bit readable/writable registers that specify the transfer request
source for each channel, together with the RS bits in each CHCRn. When the channel is not used,
or DMA transfer initiated by an auto-request or a TMU input capture interrupt is used, the
DMARSR corresponding to that channel should be set to H'00.
To resume a DMA transfer that has stopped due to an address error (AE = 1 in DMAOR) or an
NMI interrupt (NMIF = 1 in DMAOR), re-specify this register value, regardless of whether or not
a transfer request source to any channel has been changed, before specifying AE = 0 in DMAOR
or NMIF = 0 in DMAOR.
• DMARSRA
Initial value:
Initial value:
• DMARSRB
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 402 of 1330
REJ09B0554-0200
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
DMA Request Resource Selection Registers (DMARSRA, DMARSRB)
WEN
WEN
WEN
WEN
CH0
R/W
CH2
R/W
CH4
R/W
CH6
R/W
31
15
31
15
0
0
0
0
CH0
RS6
CH2
RS6
CH4
RS6
CH6
RS6
R/W
R/W
R/W
R/W
30
14
30
14
0
0
0
0
CH0
RS5
CH2
RS5
CH4
RS5
CH6
RS5
R/W
R/W
R/W
R/W
29
13
29
13
0
0
0
0
CH0
CH2
CH4
CH6
RS4
RS4
RS4
RS4
R/W
R/W
R/W
R/W
28
12
28
12
0
0
0
0
CH0
CH2
CH4
CH6
RS3
RS3
RS3
RS3
R/W
R/W
R/W
R/W
27
11
27
11
0
0
0
0
R/W
R/W
R/W
R/W
CH0
RS2
CH2
RS2
CH4
RS2
CH6
RS2
26
10
26
10
0
0
0
0
CH0
RS1
CH2
RS1
CH4
RS1
CH6
RS1
R/W
R/W
R/W
R/W
25
25
0
9
0
0
9
0
CH0
R/W
CH2
R/W
CH4
R/W
CH6
R/W
RS0
RS0
RS0
RS0
24
24
0
8
0
0
8
0
WEN
WEN
WEN
WEN
CH1
CH3
CH5
CH7
R/W
R/W
R/W
R/W
23
23
0
7
0
0
7
0
CH1
CH3
CH5
CH7
RS6
RS6
RS6
RS6
R/W
R/W
R/W
R/W
22
22
0
0
0
0
6
6
CH1
RS5
CH3
RS5
CH5
RS5
CH7
RS5
R/W
R/W
R/W
R/W
21
21
0
5
0
0
5
0
CH1
RS4
CH3
RS4
CH5
RS4
CH7
RS4
R/W
R/W
R/W
R/W
20
20
0
4
0
0
4
0
CH1
CH3
CH5
CH7
RS3
RS3
RS3
RS3
R/W
R/W
R/W
R/W
19
19
0
3
0
0
3
0
CH1
R/W
CH3
R/W
CH5
R/W
CH7
R/W
RS2
RS2
RS2
RS2
18
18
0
2
0
0
2
0
CH1
RS1
CH3
RS1
CH5
RS1
CH7
RS1
R/W
R/W
R/W
R/W
17
17
0
1
0
0
1
0
CH1
RS0
R/W
CH3
RS0
R/W
CH5
RS0
R/W
CH7
RS0
R/W
16
16
0
0
0
0
0
0