HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 371

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
15
14
13
12
11
10
Bit
Name
TRWL2
TRWL1
TRWL0
TRAS2
TRAS1
TRAS0
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Write Precharge Delay
Specify the synchronous DRAM write precharge delay in
these bits. In auto-precharge mode, specify the time
after a write cycle before the next bank active command
is issued. After a write cycle, the next active command is
not issued for a period of TPC + TRWL. In RAS down
mode, specify the time after a write cycle before the next
precharge command is issued. After a write cycle, the
next precharge command is not issued for a period of
TRWL. This setting is valid only when synchronous
DRAM interface is in use. For details on these bit
settings and the period in which no command is issued,
refer to section 33.3.3, Bus Timing.
000:
001:
010:
011:
100:
101:
110:
111:
Refresh Period
When the synchronous DRAM interface is in use, the
bank active command is not issued for a period of TRC*
+ TRAS after an auto-refresh command is issued.
000:
001:
010:
011:
100:
101:
110:
111:
Write Precharge ACT Delay Time
1
2
3*
4*
5*
Setting prohibited
Setting prohibited
Setting prohibited
Command Issuance Gap after Synchronous
DRAM Refresh
4 + TRC
5 + TRC
6 + TRC
7 + TRC
8 + TRC
9 + TRC
10 + TRC
11 + TRC
1
1
1
Rev. 2.00 Feb. 12, 2010 Page 287 of 1330
REJ09B0554-0200
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