HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 257

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.6
To enable the IC and OC to be managed by software, the IC contents can be read from or written
to by a program in the P2 area by means of a MOV instruction in privileged mode. Operation is
not guaranteed if access is made from a program in another area. In this case, a branch to the P0,
U0, P1, or P3 area should be made at least eight instructions after this MOV instruction. In
privileged mode, the OC contents can be read from or written to by a program in the P1 or P2 area
by means of a MOV instruction. Operation is not guaranteed if access is made from a program in
another area. In this case, a branch to the P0, U0, or P3 area should be made at least eight
instructions after this MOV instruction. The IC and OC are allocated to the P4 area in the physical
address space. Only data accesses can be used on both the IC address array and data array and the
OC address array and data array, and accesses are always longword-size. Instruction fetches
cannot be performed in these areas. For reserved bits, a write value of 0 should be specified; their
read value is undefined.
7.6.1
The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification. The way and entry to be accessed are specified in the address field,
and the write tag and V bit are specified in the data field.
In the address field, bits [31:24] have the value H'F0 indicating the IC address array, the way is
specified by bit [13], and the entry by bits [12:5]. The IIX bit in CCR has no effect on this entry
specification. The association bit (A bit) [3] in the address field specifies whether or not
association is performed when writing to the IC address array. As only longword access is used, 0
should be specified for address field bits [1:0].
In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address
array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which
association is not performed. Data field bits [31:29] are used for the virtual address specification
only in the case of a write in which association is performed.
The following three kinds of operation can be used on the IC address array:
1. IC address array read
2. IC address array write (non-associative)
The tag and V bit are read into the data field from the IC entry corresponding to the way and
entry set in the address field. In a read, associative operation is not performed regardless of
whether the association bit specified in the address field is 1 or 0.
The tag and V bit specified in the data field are written to the IC entry corresponding to the
way and entry set in the address field. The A bit in the address field should be cleared to 0.
Memory-Mapped Cache Configuration (Double-Size Cache Mode)
IC Address Array
Rev. 2.00 Feb. 12, 2010 Page 173 of 1330
REJ09B0554-0200