HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1408

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

E.
This LSI is provided with an internal buffer for holding pre-read instructions, and always performs
pre-reading. Therefore, program code must not be located in the last 20-byte area of any memory
space. If program code is located in these areas, the memory area will be exceeded and a bus
access for instruction pre-reading may be initiated. A case in which this is a problem is shown
below.
Figure E.1 presupposes a case in which the instruction (ADD) indicated by the program counter
(PC) and the address H'0400 0002 instruction prefetch are executed simultaneously. It is also
assumed that the program branches to an area other than area 1 after executing the following JMP
instruction and delay slot instruction.
In this case, the program flow is unpredictable, and a bus access (instruction prefetch) to area 1
may be initiated.
Instruction Prefetch Side Effects
1. It is possible that an external bus access caused by an instruction prefetch may result in
2. If there is no device to reply to an external bus request caused by an instruction prefetch,
Remedies
1. These illegal instruction fetches can be avoided by using the MMU.
2. The problem can be avoided by not locating program code in the last 20 bytes of any area.
Rev. 2.00 Feb. 12, 2010 Page 1324 of 1330
REJ09B0554-0200
misoperation of an external device, such as a FIFO, connected to the area concerned.
hangup will occur.
Instruction Prefetching and Its Side Effects
Area 0
Area 1
Address
H'03FF FFF8
H'03FF FFFA
H'03FF FFFC
H'03FF FFFE
H'0400 0000
H'0400 0002
Figure E.1 Instruction Prefetch
ADD R1,R4
JMP @R2
NOP
NOP
.
.
.
.
.
Instruction prefetch address
PC (program counter)