HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 738

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(3) Serial data reception
An example of data reception processing in smart card mode is shown in figure 18.6.
Rev. 2.00 Feb. 12, 2010 Page 654 of 1330
REJ09B0554-0200
No
No
Read received data from SIRDR
Clear RE bit in SISCR to 0
PER=0&&ORER=0
All data received?
&&WAIT_ER=0?
Start reception
Reception end
Initialization
RDRF=1?
Yes
Yes
Figure 18.6 Example of Reception Processing
Yes
No
Error processing
(1)
(2)
(3)
(4)
(5)
(6)
Note: If during reception a parity error occurs and
(1)
(2)
(3)
(4)
(5)
(6)
and initialize the smart card interface.
Confirm that the PER, ORER, and WAIT_ER flags
in SISSR are 0. If one of these flags is set, after
performing the prescribed reception error
processing, clear the PER, ORER, and WAIT_ER
flags to 0.
Repeat (2) and (3) in the figure until it can be
confirmed that the RDRF flag is set to 1.
return to step (2).
PER is set to 1, in T=0 mode the received data
is not transferred to SIRDR, and so this data
cannot be read.
Follow the procedure of item 1 in section 18.4.4,
Read received data from SIRDR.
When performing continuous data reception,
When reception is ended, clear the RE bit to 0.