HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 211

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
15 to 10 URC
9
8
7 to 3
2
1
0
Bit Name
SQMD
SV
⎯
TI
⎯
AT
Initial Value
All 0
0
0
All 0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R
R/W
Description
UTLB Replace Counter
These bits serve as a random counter for
indicating the UTLB entry for which replacement
is to be performed with an LDTLB instruction.
This bit is incremented each time the UTLB is
accessed. If URB > 0, URC is cleared to 0 when
the condition URC = URB is satisfied. Also note
that if a value is written to URC by software
which results in the condition of URC > URB,
incrementing is first performed in excess of URB
until URC = H'3F. URC is not incremented by an
LDTLB instruction.
Store Queue Mode Bit
Specifies the right of access to the store queues.
0: User/privileged access possible
1: Privileged access possible (address error
Single Virtual Memory Mode/Multiple Virtual
Memory Mode Switching Bit
When this bit is changed, ensure that 1 is also
written to the TI bit.
0: Multiple virtual memory mode
1: Single virtual memory mode
Reserved
These bits are always read as 0. The write value
should always be 0.
TLB Invalidate Bit
Writing 1 to this bit invalidates (clears to 0) all
valid UTLB/ITLB bits. This bit is always read as
0.
Reserved
This bit is always read as 0. The write value
should always be 0.
Address Translation Enable Bit
These bits enable or disable the MMU.
0: MMU disabled
1: MMU enabled
MMU exceptions are not generated when the AT
bit is 0. In the case of software that does not use
the MMU, the AT bit should be cleared to 0.
exception in case of user access)
Rev. 2.00 Feb. 12, 2010 Page 127 of 1330
REJ09B0554-0200