HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 260

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The following three kinds of operation can be used on the OC address array:
1. OC address array read
2. OC address array write (non-associative)
3. OC address array write (associative)
Rev. 2.00 Feb. 12, 2010 Page 176 of 1330
REJ09B0554-0200
The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the
way and entry set in the address field. In a read, associative operation is not performed
regardless of whether the association bit specified in the address field is 1 or 0.
The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to
the way and entry set in the address field. The A bit in the address field should be cleared to 0.
When a write is performed to a cache line for which the U bit and V bit are both 1, after write-
back of that cache line, the tag, U bit, and V bit specified in the data field are written.
When a write is performed with the A bit in the address field set to 1, the tag for each of the
ways stored in the entry specified in the address field is compared with the tag specified in the
data field. The way number set by bit [14] is not used. If the MMU is enabled at this time,
comparison is performed after the virtual address specified by data field bits [31:10] has been
translated to a physical address using the UTLB. If the addresses match and the V bit for that
way is 1, the U bit and V bit specified in the data field are written into the OC entry. In other
cases, no operation is performed. This operation is used to invalidate a specific OC entry. If the
OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If a
UTLB miss occurs during address translation, or the comparison shows a mismatch, an
exception is not generated, no operation is performed, and the write is not executed. If a data
TLB multiple hit exception occurs during address translation, processing switches to the data
TLB multiple hit exception handling routine.
Address field
Data field
Figure 7.11 Memory-Mapped OC Address Array
31
31
U
V
A
1 1 1 1 0 1 0 0
: Validity bit
: Dirty bit
: Association bit
: Reserved bits (write value should be 0, and read value is undefined )
24
23
Tag
15
14
Way
13
10 9
Entry
5 4 3 2 1 0
A
2
U
1 0
V